vishay siliconix si2308bds document number: 69958 s-83053-rev. b, 29-dec-08 www.vishay.com 1 new product n-channel 60-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 available ? trenchfet ? power mosfet ? 100 % r g tested ? 100 % uis tested applications ? battery switch ? dc/dc converter product summary v ds (v) r ds(on) ( ) i d (a) a q g (typ.) 60 0.156 at v gs = 10 v 2.3 2.3 nc 0.192 at v gs = 4.5 v 2.1 orderin g information: si230 8 bds-t1-e3 (lead (p b )-free) si230 8 bds-t1-ge3 (lead (p b )-free and halogen-free) g s d top v ie w 2 3 to-236 (ssot23) 1 si230 8 bds (l 8 )* *marking code notes: a. based on t c = 25 c. b. surface mounted on 1" x 1" fr4 board. c. t = 5 s. d. maximum under steady state conditions is 130 c/w. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 60 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 2.3 a t c = 70 c 1.8 t a = 25 c 1.9 b, c t a = 70 c 1.5 b, c pulsed drain current i dm 8 continuous source-drain diode current t c = 25 c i s 1.39 t a = 25 c 0.91 b, c avalanche current l = 0.1 mh i as 6 single-pulse avalanche energy e as 1.8 mj maximum power dissipation t c = 25 c p d 1.66 w t c = 70 c 1.06 t a = 25 c 1.09 b, c t a = 70 c 0.7 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, d 5 s r thja 90 115 c/w maximum junction-to-foot (drain) steady state r thjf 60 75
vishay siliconix si2308bds www.vishay.com 2 document number: 69958 s-83053-rev. b, 29-dec-08 new product notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. mosfet specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v ds = 0 v, i d = 250 a 60 v v ds temperature coefficient v ds /t j i d = 250 a 55 mv/c v gs(th) temperature coefficient v gs(th) /t j - 5 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 13v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 60 v, v gs = 0 v 1 a v ds = 60 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 8a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 1.9 a 0.130 0.156 v gs = 4.5 v, i d = 1.7 a 0.160 0.192 forward transconductance a g fs v ds = 15v, i d = 1.9 a 5s dynamic b input capacitance c iss v ds = 30 v, v gs = 0 v, f = 1 mhz 190 pf output capacitance c oss 26 reverse transfer capacitance c rss 15 total gate charge q g v ds = 30 v, v gs = 10 v, i d = 1.9 a 4.5 6.8 nc v ds = 30 v, v gs = 4.5 v, i d = 1.9 a 2.3 3.5 gate-source charge q gs 0.8 gate-drain charge q gd 1 gate resistance r g f = 1 mhz 0.6 2.8 5.6 tu r n - o n d e l ay t i m e t d(on) v dd = 30 v, r l = 20 i d ? 1.5 a, v gen = 10 v, r g = 1 46 ns rise time t r 10 15 turn-off delay time t d(off) 10 15 fall time t f 710.5 tu r n - o n d e l ay t i m e t d(on) v dd = 30 v, r l = 20 i d = 1.5 a, v gen = 4.5 v, r g = 1 15 23 ns rise time t r 16 24 turn-off delay time t d(off) 11 17 fall time t f 11 17 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 1.39 a pulse diode forward current a i sm 8 body diode voltage v sd i s = 1.5 a 0.8 1.2 v body diode reverse recovery time t rr i f = 1.5 a, di/dt = 100 a/s, t j = 25 c 15 23 ns body diode reverse recovery charge q rr 10 15 nc reverse recovery fall time t a 12 ns reverse recovery rise time t b 3
document number: 69958 s-83053-rev. b, 29-dec-08 www.vishay.com 3 vishay siliconix si2308bds new product typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current and gate voltage gate charge 0 2 4 6 8 10 012345 v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d v gs =10thr u 5 v v gs =2 v v gs =3 v v gs =4 v 0.06 0.12 0.1 8 0.24 0.30 0246 8 10 - on-resistance ( ) r ds(on) i d - drain c u rrent (a) v gs =10 v v gs =4.5 v 0 2 4 6 8 10 012345 i d =1.9a - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs v ds =4 8v v ds =30 v transfer characteristics capacitance on-resistance vs. junction temperature 0 1 2 3 4 0.0 0.7 1.4 2.1 2. 8 3.5 v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d t c = 125 c t c =25 c t c = - 55 c c rss 0 60 120 1 8 0 240 300 0 102030405060 c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) c oss 0.5 0. 8 1.1 1.4 1.7 2.0 - 50 - 25 0 25 50 75 100 125 150 t j -j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on) v gs =10 v ,i d =1.9a v gs =4.5 v ,i d =1.7a
vishay siliconix si2308bds www.vishay.com 4 document number: 69958 s-83053-rev. b, 29-dec-08 new product typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 t j = 150 c 1 v sd -so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s t j = 25 c 0.1 10 1.2 1.5 1. 8 2.1 2.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a ( v ) v gs(th) t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power 0.10 0.15 0.20 0.25 0.30 0.35 34567 8 910 - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) t j = 25 c t j = 125 c i d =1.9a 0 10 2 4 ) w ( r e w o p time (s) 1 600 10 6 0.1 0.01 100 t a = 25 c single p u lse 8 safe operating area v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified - drain c u rrent (a) i d 10 0.1 0.1 1 10 1 t a = 25 c single p u lse 1ms 10 ms 100 ms 0.01 1s,10s dc b v dss limited 100 100 s limited b yr ds(on) *
document number: 69958 s-83053-rev. b, 29-dec-08 www.vishay.com 5 vishay siliconix si2308bds new product typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max.) = 150 c, using junction-to-cas e thermal resistance, and is mo re useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the current rating, when this rating falls below the package limit. current derating* 0.0 0.6 1.2 1. 8 2.4 3.0 0 255075100125150 t c - case temperat u re (c) i d - drain c u rrent (a) power derating, junction-to-case 0.0 0.4 0. 8 1.2 1.6 2.0 0 25 50 75 100 125 150 t c - case temperat u re (c) po w er ( w ) power derating, junction-to-ambient 0.0 0.3 0.6 0.9 1.2 0 25 50 75 100 125 150 t a -am b ient temperat u re (c) po w er ( w )
vishay siliconix si2308bds www.vishay.com 6 document number: 69958 s-83053-rev. b, 29-dec-08 new product typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69958 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 600 10 -1 10 -4 100 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) t n e i s n a r t e v i t c e f f e d e z i l a m r o n e c n a d e p m i l a m r e h t 1. d u ty cycle, d = 2. per unit base = r thja = 130 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 1 10 10 -1 10 -4 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) t n e i s n a r t e v i t c e f f e d e z i l a m r o n e c n a d e p m i l a m r e h t
vishay siliconix package information document number: 71196 09-jul-01 www.vishay.com 1 sot-23 (to-236): 3-lead b e e 1 1 3 2 s e e 1 d a 2 a a 1 c s e a ting pl a ne 0.10 mm 0.004" c c l 1 l q g au ge pl a ne s e a ting pl a ne 0.25 mm dim millimeters inches min max min max a 0.89 1.12 0.0 3 5 0.044 a 1 0.01 0.10 0.0004 0.004 a 2 0.88 1.02 0.0 3 46 0.040 b 0. 3 5 0.50 0.014 0.020 c 0.085 0.18 0.00 3 0.007 d 2.80 3 .04 0.110 0.120 e 2.10 2.64 0.08 3 0.104 e 1 1.20 1.40 0.047 0.055 e 0.95 bsc 0.0 3 74 ref e 1 1.90 bsc 0.0748 ref l 0.40 0.60 0.016 0.024 l 1 0.64 ref 0.025 ref s 0.50 ref 0.020 ref q 3 8 3 8 ecn: s-0 3 946-rev. k, 09-jul-01 dwg: 5479
an807 vishay siliconix document number: 70739 26-nov-03 www.vishay.com 1 mounting little foot sot-23 power mosfets wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ), for the basis of the pad design for a littl e foot sot-23 power mosfet footprint . in converting this footprint to the pad set for a power device, designers must make tw o connections: an electrical connection and a thermal connection, to draw heat away from the package. the electrical connections for the sot-23 are very simple. pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. as in the other little foot packages, the drai n pin serves the additional function of providing the thermal connection from the package to the pc board. the total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. also, heat spreads in a circular fashion from the heat source. in this case the drain pin is the heat source when looking at heat spread on the pc board. figure 1 shows the footprint with copper spreading for the sot-23 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copper over lies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the ambient air. this pattern uses all the available area underneath the body for this purpose. figure 1. footprint with copper spreading 0.114 2.9 0.059 1.5 0.0394 1.0 0.037 0.95 0.150 3.8 0.081 2.05 since surface-mounted packages are small, and reflow soldering is the most common way in whic h these are affixed to the pc board, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device.
application note 826 vishay siliconix document number: 72609 www.vishay.com revision: 21-jan-08 25 application note recommended minimum pads for sot-23 0.106 (2.692) recommended mi nimum pads dimensions in inches/(mm) 0.022 (0.559) 0.049 (1.245) 0.029 (0.724) 0.037 (0.950) 0.053 (1.341) 0.097 (2.459) return to index return to index
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